Role of Self-Assembled Monolayer Passivation in Electrical Transport Properties and Flicker Noise of Nanowire Transistors

Seongmin Kim, Purdue University
Patrick D. Carpenter, Purdue University
Rand K. Jean, Purdue University
Haitian Chen, University of Southern California
Chongwu Zhou, University of Southern California
Sanghyun Ju, Kyonggi University
David B. Janes, Purdue University

Date of this Version

7-9-2012

Abstract

Semiconductor nanowires have achieved great attention for integration in next-generation electronics. However, for nanowires with diameters comparable to the Debye length, which would generally be required for one-dimensional operation, surface states degrade the device performance and increase the low-frequency noise. In this study, single In2O3 nanowire transistors were fabricated and characterized before and after surface passivation with a self-assembled monolayer of 1-octadecanethiol (ODT). Electrical characterization of the transistors shows that device performance can be enhanced upon ODT-passivation, exhibiting steep subthreshold slope (~ 64 mV/dec), near zero threshold voltage (~ 0.6 V), high mobility (~ 624 cm2/V·sec), and high on-currents (~ 40 µA). X-ray photoelectron spectroscopy studies of the ODT passivated nanowires indicate that the molecules are bound to In2O3 nanowires through the thiol linkages. Device simulations using a rectangular geometry to represent the nanowire indicate that the improvement in subthreshold slope and positive shift in threshold voltage can be explained in terms of reduced interface trap density and changes in fixed charge density. Flicker (low-frequency, 1/f) noise measurements show that the noise amplitude is reduced following passivation. The interface trap density before and after ODT passivation is profiled throughout the band-gap energy using the subthreshold current-voltage characteristics and is compared to the values extracted from the low-frequency noise measurements. The results indicate that self-assembled monolayer passivation is a promising optimization technology for the realization of low power, low noise, and fast switching applications such as logic, memory and display circuitry.

Discipline(s)

Electrical and Electronics | Electronic Devices and Semiconductor Manufacturing | Nanoscience and Nanotechnology | Nanotechnology fabrication

 

Share