Leakage-Reduction Design Concepts for Low-Power Vertical Tunneling Field-Effect Transistors

Samarth Agarwal, NCN, Purdue University
Gerhard Klimeck, NCN, Purdue University
Mathieu Luisier, NCN, Purdue University

Date of this Version

6-2010

Citation

IEEE Electron Device Lett., Vol. 31, 621-623 (2010)

Abstract

Using an atomistic full-band quantum transport solver, we investigate the performances of vertical band-to-band tunneling FETs (TFETs) whose operation is based on the enhance- ment of the gate-induced drain leakage mechanism of MOSFETs, and we compare them to lateral p-i-n devices. Although the ver- tical TFETs offer larger tunneling areas and therefore larger ON currents than their lateral counterparts, they suffer from lateral source-to-drain tunneling leakage away from the gate contact. We propose a design improvement to reduce the OFF current of the vertical TFETs, maintain large ON currents, and provide steep subthreshold slopes.

Discipline(s)

Nanoscience and Nanotechnology

 

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