Silicon Nanowire Tunneling Field-Effect Transistor Arrays: Improving Subthreshold Performance Using Excimer Laser Annealing
Date of this Version6-21-2011
J. T. Smith, C. Sandow, S. Das, R. A. Minamisawa, S. Mantl, and J. Appenzeller, IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1822-1829, Jul. 2011
We have experimentally established that the inverse subthreshold slope S of a Si nanowire tunneling field-effect transistor (NW-TFET) array can be within 9% of the theoretical limit when the doping profile along the channel is properly engineered. In particular, we have demonstrated that combining excimer laster annealing with a low-temperature rapid thermal anneal results in an abrupt doping profile at the source/channel interface as evidenced by the electrical characteristics. Gate-controlled tunneling has been confirmed by evaluating S as a function of temperature. The good agreement between our experimental data and simulation allows performance predictions for more aggresively scaled TFETs. We find that Si NW-TFETs can be indeed expected to deliver S-values below 60 mV/dec for optimized device structures.
Electronic Devices and Semiconductor Manufacturing | Nanotechnology Fabrication