3-D CMOS Circuits Based on Low-Loss Vertical Interconnects on Parylene-N

Rosa R. Lahiji, Purdue University - Main Campus
Hasan Sharifi, Purdue University - Main Campus
Linda Katehi, School of Electrical and Computer Engineering, Purdue University
Saeed Mohammadi, School of Electrical and Computer Engineering, Purdue University

Date of this Version

1-2010

Citation

DOI: 10.1109/TMTT.2009.2036394

This document has been peer-reviewed.

 

Abstract

parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15-mu m-thick parylene-N layer and 0.56 dB/mm for a 50-Omega CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with underpasses that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13-mu m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of +4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.

Discipline(s)

Engineering | Nanoscience and Nanotechnology

 

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