Characterization and Modeling of Subfemtofarad Nanowire Capacitance Using the CBCM Technique

Hui Zhao, Natl Univ Singapore
Raseong Kim, Purdue University - Main Campus
Abhijeet Paul, Purdue University
Mathieu Luisier, Purdue University - Main Campus
Gerhard Klimeck, Network for Computational Nanotechnology, Purdue University
Fa-Jun Ma, Natl Univ Singapore
Subhash Rustagi, ASTAR, Inst Microelect, Singapore
Ganesh S. Samudra, Natl Univ Singapore
Navab Singh, ASTAR, Inst Microelect, Singapore
Guo-Qiang Lo, ASTAR, Inst Microelect, Singapore
Dim-Lee Kwong, ASTAR, Inst Microelect, Singapore

Date of this Version



DOI: 10.1109/LED.2009.2015588

This document has been peer-reviewed.



The experimental characterization of gate capacitance in nanoscale devices is challenging. We report an application of the charge-based capacitance measurement (CBCM) technique to measure the gate capacitance of a single-channel nanowire transistor. The measurement results are validated by 3-D electrostatic computations for parasitic estimation and 2-D self-consistent sp(3)s*d5 tight-binding computations for intrinsic gate capacitance calculations. The device simulation domains were constructed based on SEM and TEM images of the experimental device. The carefully designed CBCM technique thus emerges as a useful technique for measuring the capacitance and characterizing the transport in nanoscale devices.


Engineering | Nanoscience and Nanotechnology