Performance Analysis of Ultra-Scaled InAs HEMTs

Neerav Kharche, Birck Nanotechnology Center and Purdue University
Gerhard Klimeck, Network for Computational Nanotechnology, Purdue University
Dae-Hyun Kim, Purdue University - Main Campus
Jesus del Alamo, Purdue University - Main Campus
Mathieu Luisier, Purdue University - Main Campus

Date of this Version

2009

Citation

ISBN: 978-1-4244-5639-0

This document has been peer-reviewed.

 

Abstract

The scaling behavior of ultra-scaled InAs HEMTs is investigated using a 2-dimensional real-space effective mass ballistic quantum transport simulator. The simulation methodology is first benchmarked against experimental I-d-V-gs data obtained from devices with gate lengths ranging from 30 to 50 nm, where a good quantitative match is obtained. It is then applied to optimize the logic performance of not-yet-fabricated 20nm InAs HEMT. It is demonstrated that the best performance is achieved in thin InAs channel devices by reducing the insulator thickness to improve the gate control while increasing the gate work function to suppress the gate leakage.

Discipline(s)

Engineering | Nanoscience and Nanotechnology

 

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