Numerical Strategies Towards Peta-Scale Simulations of Nanoelectronics Devices

Mathieu Luisier, Network for Computational Nanotechnology, Purdue University
Gerhard Klimeck, Network for Computational Nanotechnology

Date of this Version

1-25-2010

Citation

Parallel Computing 36 (2010) 117-128

Acknowledgements

This work was partially supported by NSF grant EEC-0228390 that funds the Network for Computational Nanotechnology, by NSF PetaApps grant number 0749140, and by NSF through TeraGrid resources provided by TACC and NICS. The authors would like to thank Dr. T. Minyard at TACC, Dr. B. Loftis at NICS, and Dr. D. Kothe at NCCS for providing them with full ma- chine runs on Ranger, Kraken, and Jaguar, respectively.

Abstract

We address two challenges with the development of next-generation nanotransistors, (i) the capability of modeling realistically extended structures on an atomistic basis and (ii) predictive simulations that are faster and cheaper than experiments. We have developed a multi-dimensional, quantum transport solver, OMEN, towards these goals. To approach the peta-scale, the calculation of the open boundary conditions connecting the simulation domain to its environment is interleaved with the comutation of the devic ewave functions and the work load of each task is predicted prior to any calculation, resulting in a dynamic core allocation. OMEN uses up to 147,456 cores on Jaguar with four levels of MPI parallelization and reaches a sustained performance of 504 TFlop/s, running at 37% of the machine peak performance. We investigate 3D nanowire transistors with diameters up to 10nm, reproduce experimental data of high electron mobility 2D transistors, and expect increased capabilities by using over 300,000 cores in the future.

Keywords

Nanoelectronics; Atomistic device simulations; High performance computing; Peta-scale

Discipline(s)

Engineering | Nanoscience and Nanotechnology

 

Share