Performance Limitations of Graphene Nanoribbon Tunneling FETS Due to Line Edge Roughness
Date of this Version2-22-2010
IEEE Device Research Conference, June 22-24, 2009
The functionality of tunneling field-effect transistors (TFETS) with a subthreshold slope SS better than 60 mV/dec at room temperature has recently been experimentally demonstrated. TFETs based on graphene nanoribbon (GNR) are expected to offer larger ON-currents, lower OFF-currents, and steeper SS than Si or III-V compound semiconductors, they are one-dimensional, fully compatible with planar processing, and they have light and identical conduction and valence effective masses as well as a width-tunable narrow band. However, it seems rather difficult to perfectly control the width of sub-10-nm GNRs and avoid line edge roughness (LER). Through quantitative simulation of realistically extended non-ideal structures and statistical sampling of different random configurations we can address the LER issue and guide experiments. Using a 3-D, atomistic, quantum mechanical simulator, we investigate the performance limitations of single-gate, 5.1nm-wide, p-i-n GNR TFETs with a 30nm gate. We find that source-to-drain tunneling leakage through the gate potential barrier (i) increases with LER and (ii) strongly limits the ON/OFF ratio of the devices to <1000 and SS to 25 mV>/dec, even without LER.