A Self-Aligned Process for High-Voltage, Short-Channel Vertical DMOSFETs in 4H-SiC
Date of this VersionOctober 2004
This document has been peer-reviewed.
In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to 0 5 m, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.