A Self-Aligned Process for High-Voltage, Short-Channel Vertical DMOSFETs in 4H-SiC

Maherin Martin, School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University
Asmita Saha, School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University
James A. Cooper Jr., School of Electrical and Computer Engineering, Birck Nanotechnology Center, Purdue University

Date of this Version

October 2004

Citation

DOI 10.1109/TED.2004.835622

This document has been peer-reviewed.

 

Abstract

In this paper, we describe a self-aligned process to produce short-channel vertical power DMOSFETs in 4H-SiC. By reducing the channel length to 0 5 m, the specific on-resistance of the MOSFET channel is proportionally reduced, significantly enhancing performance.

 

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