Top-gated graphene field-effect-transistors formed by decomposition of SiC

Y Q. Wu, Purdue University
P. D. Ye, Birck Nanotechnology Center and School of Electrical and Computer Engineering, Purdue University
Michael A. Capano, Birck Nanotechnology Center, Purdue University
Yi Xuan
Y Sui, Purdue Univ, Sch Elect & Comp Engn
Minghao Qi, Birck Nanotechnology Center, Purdue University
James A. Cooper, Birck Nanotechnology Center, Purdue University
T Shen, Purdue
D Pandey, Purdue University
G Prakash, Purdue University
R. Reifenberger, Birck Nanotechnology Center, Purdue University

Date of this Version

March 2008



This document has been peer-reviewed.



Top-gated, few-layer graphene field-effect transistors (FETs) fabricated on thermally decomposed semi-insulating 4H-SiC substrates are demonstrated. Physical vapor deposited SiO2 is used as the gate dielectric. A two-dimensional hexagonal arrangement of carbon atoms with the correct lattice vectors, observed by high-resolution scanning tunneling microscopy, confirms the formation of multiple graphene layers on top of the SiC substrates. The observation of n-type and p-type transition further verifies Dirac Fermions' unique transport properties in graphene layers. The measured electron and hole mobilities on these fabricated graphene FETs are as high as 5400 and 4400 cm(2)/V s, respectively, which are much larger than the corresponding values from conventional SiC or silicon.