Engineering Nanowire n-MOSFETs at L-g < 8 nm

Author

• Saumitra Mehrotra, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue UniversityFollow
• SungGeun Kim, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue UniversityFollow
• Tillmann Kubis, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue UniversityFollow
• Michael Povolotskyi, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue UniversityFollow
• Mark S. Lundstrom, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue UniversityFollow
• Gerhard Klimeck, Birck Nanotechnology Center, Network for Computational Nanotechnology, Purdue UniversityFollow

Abstract

As metal-oxide-semiconductor field-effect transistors (MOSFETs) channel lengths (L-g) are scaled to lengths shorter than L-g < 8 nm source-drain tunneling starts to become a major performance limiting factor. In this scenario, a heavier transport mass can be used to limit source-drain (S-D) tunneling. Taking InAs and Si as examples, it is shown that different heavier transport masses can be engineered using strain and crystal-orientation engineering. Full-band extended device atomistic quantum transport simulations are performed for nanowire MOSFETs at L-g < 8 nm in both ballistic and incoherent scattering regimes. In conclusion, a heavier transport mass can indeed be advantageous in improving ON-state currents in ultrascaled nanowire MOSFETs.

Keywords

InAs; nanowire; quantum transport; Si; source-drain tunneling; strain; tight-binding (TB) approach; ELECTRONICS; FETS

DOI

10.1109/TED.2013.2263806

Date of this Version

7-2013

Recommended Citation

Mehrotra, Saumitra; Kim, SungGeun; Kubis, Tillmann; Povolotskyi, Michael; Lundstrom, Mark S.; and Klimeck, Gerhard, "Engineering Nanowire n-MOSFETs at L-g < 8 nm" (2013). Birck and NCN Publications. Paper 1428.
http://dx.doi.org/10.1109/TED.2013.2263806