Limitations of the High-Low C-V Technique for MOS Interfaces With Large Time Constant Dispersion

Ashish Verma Penumatcha, Birck Nanotechnology Center, Purdue University
Steven Swandono, Birck Nanotechnology Center, Purdue University
James A. Cooper, Birck Nanotechnology Center, Purdue University

Date of this Version

3-2013

Citation

IEEE Transactions on Electron Devices ( Volume: 60, Issue: 3, March 2013 )

Comments

(c) 2013 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.

Abstract

We discuss the limitations of the high-low CV technique in evaluating the interface trap density (D-TT) in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high-low technique can seriously underestimate D-IT for samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity.

Discipline(s)

Nanoscience and Nanotechnology

 

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