Copyright (c) 2009 Purdue Libraries All rights reserved. http://docs.lib.purdue.edu/nanodocs Recent documents in Other Nanotechnology Publications en-us Thu, 13 Aug 2009 11:19:47 PDT 3600 http://docs.lib.purdue.edu/nanodocs/174 http://docs.lib.purdue.edu/nanodocs/174 Thu, 13 Aug 2009 11:13:51 PDT This paper discusses the electronic transport properties of nanowire field-effect transistors (NW-FETs). Four different device concepts are studied in detail: Schottky-barrier NW-FETs with metallic source and drain contacts, conventional-type NW-FETs with doped NW segments as source and drain electrodes, and, finally, two new concepts that enable steep turn-on characteristics, namely, NW impact ionization FETs and tunnel NW-FETs. As it turns out, NW-FETs are, to a large extent, determined by the device geometry, the dimensionality of the electronic transport, and the way of making contacts to the NW. Analytical as well as simulation results are compared with experimental data to explain the various factors impacting the electronic transport in NW-FETs. Joerg Appenzeller http://docs.lib.purdue.edu/nanodocs/173 http://docs.lib.purdue.edu/nanodocs/173 Thu, 13 Aug 2009 11:13:50 PDT In the present article we will discuss the electronic transport properties of carbon nanotube field-effect transistors (CNFETs). Three different device concepts will be studied in more detail: Schottky-barrier CNFETs with metallic source and drain contacts, conventional-type CNFETs with doped nanotube segments as source and drain electrodes and finally a new concept, the tunneling CNFET. As it turns out, tunneling phenomena play a prominent role in all three CNFET designs and determine their electrical behavior to a large extend. In addition, the one-dimensionality of the electronic transport makes them ideally suited for novel device architecture such as the tunneling CNFET. Analytical as well as simulation results will be given and compared with each other and with experimental data in order to explain the different influences on the electronic transport in CNFETs and thus on the device behavior. Joachim Knoch http://docs.lib.purdue.edu/nanodocs/172 http://docs.lib.purdue.edu/nanodocs/172 Thu, 13 Aug 2009 11:13:49 PDT We present a study on the scaling behavior of field-effect transistors in the quantum-capacitance limit (QCL). It will be shown that a significant performance improvement in terms of the power delay product can be obtained in devices scaled toward the QCL. As a result, nanowires or nanotubes exhibiting a 1-D transport are a premier choice as active channel materials for transistor devices since the QCL can be attained in such systems. Joachim Knoch http://docs.lib.purdue.edu/nanodocs/171 http://docs.lib.purdue.edu/nanodocs/171 Thu, 13 Aug 2009 11:13:48 PDT Carbon nanotube devices offer intrinsic advantages for high-performance logic device applications. The ultrasmall body of a carbon nanotube-the tube diameter-is the key feature that should allow aggressive channel length scaling, while the intrinsic transport properties of the nanotube ensure at the same time high on-currents. in addition, the narrowness of the tube is critical to implementation of novel device concepts like the tunneling transistor. By understanding the unique capabilities of carbon nanotubes and using them in unconventional designs, novel nanoelectronic applications may become feasible. However, much better control of materials quality must be obtained, and new fabrication processes must be developed before such applications can be realized. Joerg Appenzeller http://docs.lib.purdue.edu/nanodocs/170 http://docs.lib.purdue.edu/nanodocs/170 Thu, 13 Aug 2009 11:13:46 PDT In this letter, we demonstrate a gate-all-around single-wall carbon nanotube field-effect transistor. This is the first successful experimental implementation of an off-chip gate and gate-dielectric assembly with subsequent deposition on a suitable substrate. The fabrication process and device measurements are discussed in the letter. We also argue in how far charges in the gate oxide are responsible for the observed nonideal device performance. Zhihong Chen http://docs.lib.purdue.edu/nanodocs/169 http://docs.lib.purdue.edu/nanodocs/169 Thu, 13 Aug 2009 11:13:44 PDT We employ a novel multiconfigurational self-consistent Green's function approach (MCSCG) for the simulation of nanoscale Schottky-barrier-field-effect transistors (SB-FETs). This approach allows the calculation of electronic transport with a seamless transition from the single-electron regime to room-temperature FET operation. The particular improvement of the MCSCG stems from a self-consistent division of the channel system into a small subsystem of resonantly trapped states for which a many-body Fock space approach becomes numerically feasible and the rest of the system which can be treated adequately on a conventional mean-field level. The Fock space description allows for the calculation of few-electron Coulomb charging effects beyond the mean-field. We compare a conventional Hartree nonequilibrium Green's function calculation with the results of the MCSCG approach. Using the MCSCG method, Coulomb blockade effects are demonstrated at low temperatures while, under strong nonequilibrium and high-temperature conditions, the Hartree approximation is retained. Finally, the visibility of quantum and single-electron effects in scaled transistor structures is discussed. Klaus M. Indlekofer http://docs.lib.purdue.edu/nanodocs/168 http://docs.lib.purdue.edu/nanodocs/168 Thu, 13 Aug 2009 11:13:43 PDT We report on the 1/f noise in various ballistic carbon nanotube devices. A common means to characterize the quality of a transistor in terms of noise is to evaluate the ratio of the noise amplitude A and the sample resistance R. By contacting semiconducting tubes with different metal electrodes we are able to show that a small A/R value by itself is no indication of a suitable metal/tube combination for logic applications. We discuss how current in a nanotube transistor is determined by the injection of carriers at the electrode/nanotube interface, while at the same time excess noise is related to the number of carriers inside the nanotube channel. In addition, we demonstrate a substantial reduction in noise amplitude for a tube transistor with multiple carbon nanotubes in parallel. Joerg Appenzeller http://docs.lib.purdue.edu/nanodocs/167 http://docs.lib.purdue.edu/nanodocs/167 Thu, 13 Aug 2009 11:13:42 PDT We investigate electrical transport,and noise m semiconducting carbon nanotubes. By studying carbon nanotube devices with various,diameters, and contact metals, we show that the,ON-currents of CNFETs are governed by the heights of the Schottky barriers at the metal/nanotube interfaces. The current fluctuations are dominated by 1/f noise at low-frequencies and correlate with the number of transport carriers in the device regardless of contact metal. Yu-Ming Lin http://docs.lib.purdue.edu/nanodocs/166 http://docs.lib.purdue.edu/nanodocs/166 Thu, 13 Aug 2009 11:13:40 PDT The impact of the gate oxide and the silicon-on-insulator (SOI) body thickness on the electrical performance of SOI Schottky-barrier (SB) MOSFETs with fully nickel silicided source and drain contacts is experimentally investigated. The subthreshold swing S is extracted from the experimental data and serves as a measure for the carrier injection through the Sills. It is shown that decreasing the gate oxide and body thickness allows to strongly increase the carrier injection and hence, a significantly improved ON-state of SB-MOSFETs can be obtained. M Zhang http://docs.lib.purdue.edu/nanodocs/165 http://docs.lib.purdue.edu/nanodocs/165 Thu, 13 Aug 2009 11:13:39 PDT In this article we give an overview over the physical mechanisms involved in the electronic transport in ultrathin-body SOI Schottky-barrier MOSFETs. A strong impact of the SOI and gate oxide thickness on the transistor characteristics is found and explained using experimental as well as simulated data. We elaborate on the influence of scattering in the channel and show that for a significant barrier the on-state current is insensitive to scattering once the mean free path for scattering is larger than a characteristic length scale. In addition, recent efforts to lower the Schottky barrier at the source/drain channel interfaces are presented. Using dopant segregation during silicidation significantly lower effective Schottky barriers can be realized that allow for high performance SB-MOSFET devices. Joachim Knoch