Proceedings of the 12th International Conference on Simulation of Semiconductor Devices and Processes (SISPAD), Vienna Austria.


As device sizes shrink towards the nanoscale, CMOS development investigates alternative structures and devices. Existing CMOS devices will evolve from planar to 3D non-planar devices at nanometer sizes. These devices will operate under strong confinement and strain, regimes where atomistic effects are important. This work investigates atomistic effects in the transport properties of nanowire devices by using a nearest-neighbor tight binding model (sp3s*d5-SO) for electronic structure calculation, coupled to a 2D Poisson solver for electrostatics. This approach will be deployed on as an enhancement of the existing Bandstructure Lab.

Date of this Version

September 2007