Designing reliable CMOS chips involve careful circuit design with attention directed to some of the potential reliability problems such as electromigration and hot carrier effects. This paper considers logic synthesis to handle electromigration and hot carrier degradation early in the design. phase. The electromigration and the hot carier effects are est,imated at the gate level using signal activity measure, which is the average number of transitions at circuit nodes. Logic can be optimally synthesized suited for different applications requiring different types of inputs for higher reliability and low silicon area. Results have been obtained for MCNC synthesis benchmark examples.
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