Fully-depleted single-gated and dual-gated SOI MOSFETs are fabricated using both Epitaxial Lateral Overgrowth (ELO) and Confined Lateral Selective Epitaxial Growth (CLSEG). SOI MOSFETs and diodes are fabricated in thin (= 1500A) CLSEG films grown in pre-defined 2500A, thick cavities for the first time. In addition to the SOI MOSFETs fabricated using selective epitaxial growth, thin-film SO1 MOSFETs were also fabricated on SIMOX wafers. The one to one comparison between the two SOI technologies proves that the EL0 and CLSEG material is of at least as good if not better quality than that of SIMOX. Effective hole mobilities in the excess of 300 cm2/V-sec were obtained on thin-film EL0 and pp,eff values of greater than 240 cm2/V-sec were extracted from the thin-film CLSEG devices. A new linear sweep technique to measure generation lifetimes in thin SOI films has been developed. The measurement technique uses fully-depleted or partially depleted MOSFETs as the test structure. A detailed analytical formulation that involves the solution of Poisson's equation as applied to a fully-depleted SOI structure is presented. The analytical solutions are used to simulate the behavior of the SOI devices under the proposed linear sweep conditions. Finally, the linear sweep technique is applied to fullydepleted devices fabricated on SIMOX material and an average lifetime of 2μs is extracted from devices across the waCer. The effects of volume inversion in thin-film short-channel SO1 MOSFETs and the efficacy of dual-gate operation in enhancing their device performance have been analyzed using two dimensional device simulations and one-dimensional analytical computations. In the strong inversion regime, the analyses suggest that when compared at constant VG VT values, the dual-channel volume inverted devices do not offer significant currentenhancement advantges, other than that expected from the second channel, over the conventional single-channel devices for silicon film thicknesses in the 0.1μm range. In its support however, two-dimensional simulations suggest that dual-gated devices are more immune to short channel effects than conventional single-gated devices. In this regard, a novel process sequence to fabricate self-aligned dual-gated MOSFETs is presented.
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