This paper presents accurate estimation of signal activity at the internal nodes of combinational logic circuits. The methodology is based on stochastic model of logic signah and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinationa1l ogic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucia1 to balance a11 signa1 paths and to reduce the logic depth . As a.result of balancing delays through different paths the inputs to logic gates may switch at approximately the same time. We have developed and implementated two algorithms to calculate signal probability and switching activity. The first technique considers signal correlations without considering such switching. Experimental results for the technique show that the swithing activity if the internal notles can be off by more than 100% compared to simulation based techniques. However the latter technique is within 5% of logic simulation results. Formal proof of correctness of our method has been presented.
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