Cache miss rates are quoted for a specific program, cache configuration, and input set; the effect of program layout on the miss rate has largely been ignored. We examine the variation of the miss rate resulting from randomly chosen layouts, the miss variation, for several cache configurations (cache size, lines size, and set-associativity), input sets, and optimization levels for five programs in the SPEC benchmark suite. We observed miss rates that varied from 0.6m to 1.8m, where m is the mean miss rate. We did not observe any consistently good layouts across different parameters; in contrast, several layouts were consistently bad. Overall, cache line size has little effect on the miss variation, while increasing the cache size (decreasing the miss rate), decreasing the set-assaciativity, or increasing the optimization level increased the miss variation. We question the validity of using a single layout to represent the miss rate of a given program for a directmapped cache.

Date of this Version

June 1995