This paper presents a new family of logic gates for ultra low energy computing using pulsed power CMOS logic. The logic gates use the principles of adiabatic switching principle and results show that in typical cases 90% of the energy can be recovered with operating frequency around IMHz. Constant capacitance condition is enforced in our designs so that signals' energy can be efficiently recycled in the chip. We also present a detailed analysis and modeling of energy dissipation. The models were experimentally validated using the circuit simulator SPICE. We also simulated a serial adder (mod 2) implemented using the reversible logic principle. The design can recover 85% of energy while operating at a frequency of 1.67MHz. For a naturally reversible buffer chain, 95% of energy can be recovered at 1.1 MHz.

Date of this Version

March 1995