Proceedings - International Test Conference (2008) IEEE Computer Society Test Technology Technical Council; IEEE Philadelphia Section-IEEE Computer Society Test Technology Technical Council; IEEE Philadelphia Section;
In this work, we propose a novel low power, process tolerant, generic and reconfigurable test structure to reduce the test cost, improve diagnosability and verifiability of complex VLSI systems. The test structure contains a variety of configurable design-for-test units designed with low cost Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs) that are fabricated on a separate substrate (e.g., polymer, glass etc). The proposed test circuits do not consume any silicon area because they can be integrated on the chip using 3-D technology. This reconfigurable test paradigm eliminates the need to re-design the BIST components that may vary from one processor generation to another.
design for testability, Polycrystalline materials, Polysilicon, thin film transistors, VLSI circuits
Date of this Version