Proceedings of the Custom Integrated Circuits Conference (2008) 419-422;
Cell stability and tolerance to process variation are of primary importance in subthreshold SRAMs. We propose a DTMOS based 6T SRAM suitable for subthreshold operation. For variation tolerant memory peripheral circuitry, we apply -ratio modulation technique. DTMOS SRAM array fabricated in 90nm technology operates down to 135mV consuming 0.13W at 750Hz. The proposed SRAM achieves 200% improvement in read static noise margin at iso-area compared to the conventional 6T SRAM at a supply voltage of 200mV.
integrated circuit layout, Integrated circuits, Modulation, nanotechnology, Static random access storage
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