Accurate power estimation in low -voltage digital CMOS with applications to circuit design and testing
Due to the recent trend toward highly reliable portable computing and wireless communications systems, power dissipation in VLSI systems is of critical importance. The existing dynamic power estimation techniques require accurate description of input signal distribution. However, accurate input signal specification may not often be available. Due to the strong dependence of power dissipation on signal distribution, uncertainties in specification of input signals lead to uncertainties in average power. Therefore, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use existing power estimation techniques to determine such bounds. We present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to primary inputs. We have implemented two novel techniques to estimate sensitivities: a probabilistic technique and a statistical technique, in which the sensitivities can be obtained as a by-product of average power estimation. Based on power sensitivity, a novel power macromodel has been proposed for high level power estimation. Compared to existing macromodeling techniques, a power surface is approximated by planes instead of discrete points, resulting in improved accuracy. ^ The existing power estimation tools also assume that the leakage component of power dissipation is negligible. However, the scaling of device threshold voltage in low voltage low power circuits leads to a dramatic increase in leakage power due to the exponential relationship between leakage current and threshold voltage in the weak inversion region of operation. We have implemented a genetic algorithm based technique to estimate the minimum (and maximum) leakage power dissipation. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50%. Leakage power can also be reduced using multiple transistor threshold voltages. The decrease in leakage current using such leakage control techniques may benefit IDDQ testing of low voltage CMOS circuits. We investigated the possibilities of applying dual threshold and vector selection techniques to improve the fault coverage of IDDQ testing. Results on a large number of benchmarks indicate that such leakage control techniques are very effective in significantly improving fault coverage. ^
Major Professor: Kaushik Roy, Purdue University.
Engineering, Electronics and Electrical