An optimized silicon carbide power UMOSFET

Jian Tan, Purdue University

Abstract

This thesis concentrates on building a power UMOSFET on SiC. The major problem of the Conventional UMOSFET is that the bottom trench oxide breaks down before avalanche breakdown occurs in the SiC. This restricts the full usage of the SiC high avalanche field property. A novel structure Protected UMOSFET for protecting the bottom trench oxide and increasing blocking voltage is analyzed. Simulation shows that the protected UMOSFET increases the blocking voltage but also increases the on-resistance as it introduces a JFET resistance. A trade-off problem exists for designing the trench depth: if the trench is too deep, the protection effect is lost, if too shallow, on-resistance increases or pinch-off happens. Another novel structure, called Optimized UMOSFET, is proposed to solve this trade-off problem. Simulation shows the Optimized UMOSFET not only has the ideal blocking voltage but also lower on-resistance than the conventional UMOSFET. Some design issues as well as fabrication issues are discussed. Actual device fabrication shows a low inversion layer mobility. The low inversion layer mobility is partially avoided by using an Accumulation Layer in the channel. Measurement results of the Conventional UMOSFET, Protected UMOSFET, Optimized UMOSFET, and Accumulation Layer Optimized UMOSFET are presented along with detail discussions. Nearly ideal blocking voltage is achieved in real devices, and the forward on-resistance is 20 times lower than theoretical Si devices designed with the same blocking voltage. In order to get the theoretical SiC performance, channel mobility needs further improvement. Future research is suggested to push the power UMOSFET to its SiC theoretical limit.

Degree

Ph.D.

Advisors

Cooper, Purdue University.

Subject Area

Electrical engineering

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