Design optimizations to facilitate reduction of supply voltage and threshold voltage in CMOS logic

Mark Casey Johnson, Purdue University

Abstract

Growth in the speed and integration density of CMOS digital systems far outpaces the growth in battery life and physical packaging limits. Voltage reduction promises substantial energy savings, by virtue of the square law relationship between power and voltage. However, low supply voltage also leads to both higher circuit delays and higher leakage current as transistor thresholds are lowered to maintain performance. Timing and resource utilization imbalances limit opportunities to use a lower supply voltage. Multiple voltage design alleviates this constraint by permitting circuitry that is not in a critical path to run at reduced voltages. In data path designs, one can optimize the schedule of operations and resource utilization to obtain the greatest benefit from multiple voltages. Integer Linear Programming (ILP) and heuristic optimization techniques were used to show that even if a single supply voltage is lowered to the minimum, there are often still opportunities to reduce energy on the order of 20% to 50%. Leakage indirectly limits opportunities to use reduce supply voltages. It is not possible to lower the operating voltage indefinitely without lowering the threshold voltage to maintain performance. This can increase leakage by several orders of magnitude. When a circuit is idle, leakage can be alleviated by applying input vectors which minimize the leakage of the circuit. Algorithms and a circuit level leakage model were developed in order to be able to choose minimum leakage inputs. For most circuits, the minimum leakage input vector alone reduces leakage by less than 50%. For those gates which are not in a low leakage state and are not in a critical delay path, a leakage control transistor can be inserted between the logic gate and the power or ground rail. Analyzing this last technique, we found leakage levels that were at least 50% and as much as 90% lower than the minimum leakage obtained by input vector selection alone.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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