Analog integrated circuit design issues using 6H-silicon carbide CMOS technology
Abstract
The objective of this research is to address the design issues of integrated circuits using 6H silicon carbide (SiC) technology. Because of its wide bandgap (3.0 eV for 6H-SiC), high thermal conductivity, and high breakdown electric field strength, integrated circuits fabricated using SiC can provide significant benefits in such areas as engine sensors and controllers for the automobile and aircraft industries, and power switching devices for the power industry. Since SiC integrated circuits are intended for operation at elevated temperatures, their performance, especially analog circuits, whose performance is more sensitive to temperature variations, must provide stable operation over a wide range of temperatures. In addition, due to the infancy of SiC technology, the fabrication process can not be well-controlled. Accordingly, the circuit performance must be resistant to large process variations. Using the operational amplifier (OPAMP), which is the most pervasive analog component, we propose several key building blocks that make the OPAMP performance stable over a wide range of temperature and process variations. First of all, a bias circuit is developed that renders the low frequency voltage gain of the OPAMP insensitive to temperature and process variations in both threshold voltage and carrier mobility. Furthermore, to prevent the maximum input common mode range from being only 50% of the power supply voltage, especially if the OPAMP is used as a unity-gain buffer, an N-channel differential pair and a P-channel differential pair are used in parallel to form the complementary input stage such that both the input and the output voltages can achieve full rail-to-rail voltage swings. To ensure that the total transconductance of the complementary input stage can be kept almost constant over the input common mode range, a novel bias circuit is proposed. Also, this scheme is not dependent on the transconductance parameter matching between the NMOS and PMOS transistors, thus resolving the problem of process variations, which may be as high as 100% in the current SiC technology. The adaptive biasing schemes are employed in the output stage to produce a full rail-to-rail output voltage swing and a low output resistance. To take process variations in the fabricated capacitors into account, a tunable frequency compensation structure is proposed, thus offsetting process variations and keeping the phase margin invariant. Finally, these concepts culminate in an intelligent gate drive circuit which can be used to provide sensing/protection functions for a power electronic building block.
Degree
Ph.D.
Advisors
Kornegay, Purdue University.
Subject Area
Electrical engineering
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