Basic MOS studies for silicon carbide power devices

Jayarama Narayan Shenoy, Purdue University

Abstract

This thesis focuses on basic MOS research on SiC and the design of high voltage MOS devices on SiC with high field stressing of the gate oxide as the main criterion. These are identified as the areas where the most contributions could be made to the field of silicon carbide power MOS switching devices. Electrical characterization of the SiC/SiO$\sb2$ interface is the first topic developed in this thesis and a variety of MOS characterization techniques are applied to silicon carbide and compared with each other. A baseline gate oxidation process is developed for 6H- and 4H-SiC. The optimization efforts for this thermal oxidation step result in the lowest effective fixed charge (8.5 $\times$ 10$\sp{11}$ cm$\sp{-2}$) and midgap interface state density (1.5 $\times$ 10$\sp{11}$ cm$\sp{-2}$eV$\sp{-1}$) reported so far on p-type 6H-SiC. Several effects of doping, substrate orientation, and processing are studied in this research. The UMOS structure is identified by other groups as the power MOSFET structure of choice for silicon carbide. MOS studies done here indicate inferior properties for the gate oxide in that structure, and simulations identify a severe enhancement in high-field stressing in the gate oxides of SiC UMOSFETs. A Double-Implant MOS (DIMOS) process is proposed to realize a planar structure that minimizes these drawbacks. The first SiC DIMOS transistors are fabricated and demonstrated in 6H-SiC as the final part of this thesis. These transistors attain breakdown voltages of over 750 V, which is about a factor of three improvement over current SiC UMOS transistor results.

Degree

Ph.D.

Advisors

Melloch, Purdue University.

Subject Area

Electrical engineering

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