A CAPABILITY ARCHITECTURE

THOMAS DONALD DENNIS, Purdue University

Abstract

This thesis examines the feasibility of using a tagged memory and a stack processor to implement a capability based computer. The hypothesis put forth here is that these two architectural features reduce the cost of the capability mechanism and result in a simpler implementation. We begin by motivating memory protection and protection systems as a basic need of modern computer systems. A brief historical survey is presented which begins with Dennis and Van Horn's paper on the semantics of multi-programmed computations and ends with a review of the major capability machines which resulted from this paper.^ We then introduce the memory and processor organization proposed for this design and compare this organization with that used in previous architectures. This discussion shows that a tagged-memory organization reduces the number of segments used by a process by allowing segments to contain both pointer and data information. This reduces memory management overhead and allows a simpler representation of objects. Moreover, the tagged memory simplifies the mechanisms used to change domains, pass parameters, and address information in primary memory. The stack processor is shown to further reduce the cost of the capability mechanism by providing an inexpensive way to allocate procedure activation records, handle domain changes, and address objects on the stack.^ Next we present the capability mechanism for the proposed design and discuss the process of mapping capability based virtual addresses into absolute primary memory addresses, and show how the abstract type concept is directly supported by the capability mechanism.^ A discussion of the hardware facilities needed to support the design follows. This discussion presents a detailed view of the registers of the central processor, the organization of the process stack, the instruction set, and a possible firmware organization which could be used to implement the design.^ The proposed architecture is then compared with two conventional machines and shown to be more efficient in representing programs. Moreover, evidence is presented which suggests that the performance of the proposed machine would be competitive with current state-of-the-art machines. Finally, two examples are presented which use the abstract type, process synchronization, and process communication facilities provided by the design.^ The major contribution of this thesis is the thorough examination it provides of the tagged memory approach to capability addressing. Out research shows a tagged-memory capability machine is powerful enough to implement an operating system and the resulting operating system has a complexity about equal to that of the older generation of simple systems with little memory protection. This thesis also illustrates that advanced programming concepts can be implemented quite simply if the proper hardware support is provided. Finally, we show that the process control mechanism introduced in this thesis removes an important source of memory contention from the mutual exclusion mechanism. This is seen as a partial solution to the memory contention problem found on many multi-processor systems. ^

Degree

Ph.D.

Subject Area

Computer Science

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