Silicon, germanium, and III-V-based tunneling devices for low-power applications

Joshua T Smith, Purdue University

Abstract

While the scaling of transistor dimensions has kept pace with Moore's Law, the voltages applied to these devices have not scaled in tandem, giving rise to ever-increasing power/heating challenges in state-of-the-art integrated circuits. A primary reason for this scaling mismatch is due to the thermal limit—the 60 mV minimum required at room temperature to change the current through the device by one order of magnitude. This voltage scaling limitation is inherent in devices that rely on the mechanism of thermal emission of charge carriers over a gate-controlled barrier to transition between the ON- and OFF-states, such as in the case of conventional CMOS-based technologies. To overcome this voltage scaling barrier, several steep-slope device concepts have been pursued that have experimentally demonstrated sub-60-mV/decade operation since 2004, including the tunneling-field effect transistor (TFET), impact ionization metal-oxide-semiconductor (IMOS), suspended-gate FET (SG-FET), and ferroelectric FET (Fe-FET). These reports have excited strong efforts within the semiconductor research community toward the realization of a low-power device that will support continued scaling efforts, while alleviating the heating issues prevalent in modern computer chips. Literature is replete with claims of sub-60-mV/decade operation, but often with neglect to other voltage scaling factors that offset this result. Ideally, a low-power device should be able to attain sub-60-mV/decade inverse subthreshold slopes (S) employing low supply and gate voltages with a foreseeable path toward integration. This dissertation describes the experimental development and realization of CMOS-compatible processes to enhance tunneling efficiency in Si and Si/Ge nanowire (NW) TFETs for improved average S (S avg) and ON-currents (ION), and a novel, III-V-based tunneling device alternative is also proposed. After reviewing reported efforts on the TFET, IMOS, and SG-FET, the TFET is highlighted as the most promising low-power device candidate, owing to its potential to operate within small supply and gate voltage windows. In a critical analysis of the TFET, the advantages of 1-D systems, such as NWs, that can potentially access the so-called quantum capacitance limit (QCL) are discussed, and the remaining challenges for TFETs, such as source/channel doping abruptness, and material tradeoffs are considered. To this end, substantial performance improvements, as measured by Savg and ION, are experimentally realized in top-down fabricated Si NW-TFET arrays by systematically varying the annealing process used to enhance doping abruptness at the source/channel junction—a critical feature for maximizing tunneling efficiency. A combination of excimer laser annealing (ELA) and a low-temperature rapid thermal anneal (LT-RTA) are identified as an optimum choice, resulting in a 36% decrease in Savg as well as ∼500% improvement in ION over the conventional RTA approach. Extrapolation of these results with simulation shows that sub-60-mV/decade operation is possible on a Si-based platform for aggressively scaled, yet realistic, NW-TFET devices. Back-gated NW-FET measurements are also presented to assess the material quality of Ge/Si core/shell NW heterostructures with an n+-doped shell, and these NWs are found to be suitable building blocks for the fabrication of more efficient TFET systems, owing to the very abrupt doping profile at the shell/core (source/channel) interface and smaller bandgap/effective mass of the Ge channel. Finally, low current levels in conventional TFETs have recently led researchers to re-examine III-V heterostructures, particularly those with a broken-gap band alignment to allow a tunneling probability near unity. Along these lines, a novel tunnel-based alternative is presented—the broken-gap tunnel MOS—that enables a constant S < 60 mV/decade. The proposed device permits the use of 2-D device architectures without degradation of S given the source-controlled operation mechanism, while simultaneously avoiding undesirable nonlinearities in the output characteristics.

Degree

Ph.D.

Advisors

Appenzeller, Purdue University.

Subject Area

Electrical engineering|Nanotechnology

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