On-chip memory design in scaled technologies
Abstract
In order to enhance performance and to support highly integrated functions, on-chip memory area has increased every technology generation. However, increased effect of parametric variations, susceptibility to soft errors, and increased leakage current in scaled technologies pose significant challenges in the design of low-power robust on-chip memory. In addition, there are application-specific design requirements. This research addresses the aforementioned issues related to on-chip memories to achieve robustness as well as optimality in terms of design requirements. Soft errors are especially important in Field Programmable Gate Arrays (FPGAs). In particular, soft errors in programming memory, leads to incorrect functionality in FPGAs. We present soft-error-tolerant FPGA operations using a new built-in 2-dimensional Hamming product code. Next, we propose a wide-range Voltage-Frequency-Scaling (VFS) Viterbi decoder using a novel traceback memory. Considering memory access patterns specific to Viterbi traceback, along with low-voltage array design, highly energy-efficient Viterbi decoder operation with wide-range of VFS is achieved. For general purpose computing, we first focus on on-chip SRAM cache design for energy-efficient high-performance operation. We present a 1R/1W multi-port 8T-SRAM array with column selection that enables supply-voltage-scalable set-associative caches with 1R/1W multi-port. The proposed technique addresses the limitation of a conventional 8T SRAM in which column selection prevents multi-port operation and vice versa. Finally, we consider Spin-Transfer Torque Magnetic RAM (STT-MRAM) as an alternative to SRAMs for future processors. A detailed analysis of energy-efficiency, area, and performance in comparisons to SRAM caches is carried out. It is shown that STT-MRAM cache has significant energy and performance benefits in low level cache hierarchy. In order to address excessive write-energy requirement of STT-MRAM, we propose a new cache architecture performing partial-line-update. The proposed architecture provides significant write-energy reduction, which can potentially make STT-MRAM suitable for on-chip caches.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Computer Engineering|Electrical engineering
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