Atomic-layer-deposited high-k dielectric/III-V semiconductor integration for future non-silicon CMOS applications

Min Xu, Purdue University

Abstract

Si-based CMOS devices have been successfully scaling down for decades to meet Moore’s Law. With higher operating frequency and larger integration density in a single chip, the power density is becoming a more and more serious issue. Therefore, power-constraints are the major concern for future transistor engineering. Power density is proportional to the operating voltage squared, indicating power density can be greatly reduced by using low voltage. III-V materials are the promising solutions because they inherently have very high carrier velocity at low electric field, which means the transistors can maintain high performance at low operating voltage, using reduced power. However, it poses many difficult challenges, among which perhaps the most difficult problem is the fermi-level pinning at the gate dielectric/III-V interface. An effective methodology based on low-temperature C-V analysis was developed to understand the electrical behaviors of high-k/III-V system. By applying this methodology, a new material system – (111)A surface oriented III-V, was explored for NMOSFET applications. Meanwhile, to meet the less than 1nm EOT requirement, processes using epitaxial high- k gate dielectrics (LaLuO3, LaYO3) grown by atomic layer deposition (ALD) were developed in close collaboration with researchers at Harvard University. In order to implement III-V CMOS technology, suitable III-V materials for PMOSFET devices were also investigated. Based on charge-neutral-level (CNL) alignment and low-temperature C-V analysis, Sb-based materials were chosen for III-V PMOSFETs development. With low-temperature ALD Al2O 3 gate dielectric, a high-performance III-V PMOSFET was demonstrated on n-GaSb substrate. Finally, a couple of integration issues were discussed for the III-V CMOS realization.

Degree

Ph.D.

Advisors

Ye, Purdue University.

Subject Area

Electrical engineering

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