MOSFET degradation due to negative bias temperature instability (NBTI) and hot carrier injection (HCI), and its implications for reliability-aware VLSI design
Abstract
The scaling trends in CMOS technology and operating conditions give rise to serious degradation mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) in MOSFETs, threatening the circuit and product lifetimes. The aging phenomena, on top of process variations, translate into complexity and reduced design margin for circuits. International Technology Roadmap for Semiconductors mentions reliability as one of the "Design Technology Challenges" and calls attention to "Design for Reliability." In order to increase the overall design efficiency, it is important to (i) understand MOSFET-level degradation, (ii) develop physically robust compact models compatible with circuit simulators, and (iii) implementing tools that incorporate NBTI and HCI reliability into VLSI design process at an early stage. In this work, NBTI and HCI degradation and their implications on MOSFET and circuit reliability are studied. Transistor-level NBTI degradation is explored and experimentally calibrated voltage, temperature, and time dependences are obtained. Recovery characteristics, degradation under AC and random activity relations are derived. Implications for aggressively-scaled and non-planar MOSFET geometries are discussed. With comprehensive experimental and theoretical tools, HCI degradation is investigated, particularly for short channel MOSFETs with lower operating conditions. HCI issues that are unclear in the literature are resolved. The interface trap generation under HCI is linked to NBTI theory, thus degradation of circuits experiencing both mechanisms can be assessed efficiently. Finally, compact reliability models for MOSFETs are presented so that this framework can be applied to digital and analog circuits as well as memory circuits.
Degree
Ph.D.
Advisors
Alam, Purdue University.
Subject Area
Electrical engineering
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