High quality tests for transition faults

Hangkyu Lee, Purdue University

Abstract

Given the rapid increase in the clock frequency of integrated circuits, the quality requirements of high-speed design necessitate delay fault testing. Transition faults are often used as a delay fault model due to the feasibility of test pattern generation and fault simulation for this model. In this thesis, we propose methodologies of generation and selection of high quality tests for transition faults. We first describe a new procedure of generating high quality weighted random patterns based on Markov sources for scan BIST targeting transition faults. We initially use statistics of deterministic tests for stuck-at faults in the design of a Markov source for transition faults. Then, by using statistics of tests for transition faults, we detect all the remaining detectable transition faults. Next, we propose and evaluate two metrics for selection of high quality delay tests out of a large given set of tests. In the path-based approach, we check the input transition patterns of each gate on an excited path and assign larger metric values to gates with a possibility of increased delays due to off-path inputs. In the cone-based approach, we trace the transitions from the inputs to the outputs of each cone in a circuit and perform a simple dynamic timing analysis to estimate a worst case delay. We then present a test generation procedure for transition faults that minimizes the detection of redundant transition faults in order to reduce unnecessary yield loss. We also propose rules for identifying dominance relations between redundant transition faults and detectable transition faults. We next propose a procedure of generating functional broadside tests for transition faults to further reduce unnecessary yield loss due to non-functional operation conditions of transition fault testing. The new test generation procedure consists of two phases and each phase uses a distinct strategy to generate functional broadside tests. The first phase uses simulation-based techniques and constrained test generation techniques. In the second phase, we apply a complete method using a sequential test generator for faults aborted in the first phase.

Degree

Ph.D.

Advisors

Pomeranz, Purdue University.

Subject Area

Electrical engineering

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