Designing robust and low -leakage VLSI circuits at the end of silicon roadmap: Technology and circuit perspectives

Saibal Mukhopadhyay, Purdue University

Abstract

CMOS devices have been scaled down aggressively in last few decades resulting in higher integration density and improved performance. However, due to short channel effects, threshold voltage scaling, oxide thickness scaling and increased doping density, the off current in the devices has increased drastically with technology scaling. Hence, as we are approaching the end of the silicon roadmap, controlling the leakage current is becoming a major problem. Moreover, the statistical variation in process parameters, such as device structure (channel length, oxide thickness, width etc), location and number of dopants in channel (random dopant effects), is increasing with technology scaling. The variation in process parameters results in a large variation performance and leakage of a circuit, and significantly reduces its robustness. In this research, we address the problem of designing low-leakage and process variation tolerant VLSI circuits in sub-100nm single gate and multiple gate silicon technologies. Analytical models and estimation tools are developed to compute leakage in logic and memory circuits. Using these models, we propose a device-aware transistor stacking technique to reduce standby leakage in logic circuits. The effects of parameter variation on device leakage current are analyzed in detail. The random intrinsic fluctuations in small devices (such as random dopant fluctuations, RDF) significantly reduce stability of Static Random Access Memory (SRAM) cell and degrade memory yield. We develop analysis/estimation methods of parametric failures, explored device/circuit optimization possibilities for better cell stability, and proposed post-silicon self-repair technique to improve SRAM yield. The leakage estimation/reduction methods and process variation tolerant SRAM design techniques are developed for multiple-gate transistors. We show the effectiveness of using independent gate controls in multiple gate transistors for low-power, high-performance, and robust circuit design.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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