Reducing test application time for scan circuits using limited scan operations
Abstract
The test application time of a scan circuit is a significant factor in the overall test cost of the circuit. Therefore, reducing the test application time is an important problem. The test application time of a test set for a scan circuit is determined by the sum of the number of scan shifts required for applying the test set, and the number of primary input vectors in the test set. Compaction procedures that view a full scan circuit as a combinational circuit reduce the number of test vectors, where a test vector consists of a scan vector and a primary input vector. This is not sufficient since for large scale circuits the high test application time is a result of the number of scan operations (or scan vectors) rather than the number of primary input vectors. Therefore, effective procedures must reduce the number of scan operations further than the combinational circuit view allows. Procedures to reduce the test application time by dropping scan operations have been proposed earlier. The compaction procedures proposed in this research reduce the test application time further by using limited scan operations. Under a limited scan operation, the number of shifts is smaller than the length of a scan chain. Static compaction procedures and dynamic compaction procedures which use limited scan operations are proposed. In the proposed static compaction procedures a test set generated by a test generation procedure is compacted using limited scan operations. In the proposed dynamic compaction procedure a test set is not required as input, and the compaction process is carried out as part of a test generation procedure.
Degree
Ph.D.
Advisors
Pomeranz, Purdue University.
Subject Area
Electrical engineering
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