Exploring device and circuit architecture for scaled technologies

Cassondra Lynn Crotty Neau, Purdue University

Abstract

The continued scaling of bulk MOSFET device dimensions results in an increase in device leakage and an increase in variations in the device parameters. In sub-90nm technologies, device leakage will no longer be dominated by sub-threshold leakage currents as gate leakage and source/substrate and drain/substrate junction band-to-band tunneling currents increase with each technology generation. Traditionally much of the leakage power reduction effort has centered on sub-threshold leakage reduction techniques. The effectiveness of common leakage techniques such as stacking and reverse body bias will be reduced as sub-threshold leakage contributes a smaller percentage of the total leakage current. We propose a new paradigm for leakage power reduction. By monitoring the individual leakage components, total leakage power can be reduced with appropriate leakage component trade-offs. We introduce a new stacking technique of input vector selection based on the relative contributions of sub-threshold leakage and gate leakage. We also propose a new optimal body bias selection technique based on the relative contributions of sub-threshold leakage and junction band-to-band tunneling. In addition to lowering total leakage, the optimal body bias selection technique is also an effective method for process variation compensation. Since these leakage reduction techniques weigh the relative contributions of leakage components, they reflect the changing requirements as technologies scale.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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