Circuit design for silicon -on -insulator (SOI) CMOS technologies

Jae-Joon Kim, Purdue University

Abstract

As the scaling of CMOS technologies approaches the end of the roadmap, interests in alternative CMOS devices to replace the conventional bulk CMOS is growing. Partially depleted silicon-on-insulator (PD/SOI) is a strong contender for high performance digital circuits, thanks to its good manufacturability and compatibility with bulk CMOS. In the long run, however, double gate (DG) fully depleted SOI MOSFET is believed to be the most promising candidate for an ultimate solution to CMOS scaling. To maximize the benefits of the new device technologies in circuit design, advantages in each device should be exploited while unique problems absent in bulk CMOS should be controlled. In the first part of the research, we develop circuit styles to control the floating body effect which is a unique characteristic in PD/SOI. In addition, we propose a sense-amp based differential circuit style to maximize the advantage of PD/SOI. We apply the circuit technique to design a modular 64-bit adder. In the second part of the research, we discuss the potential of DG MOSFET for ultra-low power digital sub-threshold circuit operation due to its smaller gate capacitance as well as higher current in sub-threshold region. The results of investigation on the optimal device characteristics for DG MOSFET sub-threshold operation show that device with longer channel length (compared to minimum gate length) can be used for robust sub-threshold operation without loss of performance. It is also shown that the source and drain structure of DG MOSFET can be simplified for sub-threshold operation since source and drain need not be raised to reduce the parasitic resistance.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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