Analysis and design of CMOS VLSI considering uncertainties in circuit parameters
Abstract
Continuous scaling of high performance CMOS circuits creates a plethora of noise/reliability effects that are potentially endangering the design margins. Crosstalk noise and process parameter variation are main concerns among them. In addition, the variation in gate delay due to simultaneous input switching can not be accurately modeled by conventional methods. In this thesis, various circuit analysis and design techniques are presented for these uncertainties in CMOS VLSI. First, a noise model is proposed for dynamic circuits to analyze functional failures considering both capacitive and inductive coupling. The model is improved to further reduce the pessimism in analyzing crosstalk noise effects by considering keeper transistor in DOMINO circuits. Different noise models are compared and the pessimism is quantified by defining failure coverage and false alarms. A solution is also provided to the problem of signal alignment for timing verification under crosstalk noise. Unlike the functional failure, timing failure can occur in both static and dynamic circuits. Second, a methodology is proposed to accurately capture the gate delay variation under simultaneous input switching. Input signals are aligned based on the proposed method and worst delay is calculated with minimal simulation efforts. Finally, a sizing algorithm is presented for the improvement in yield under process parameter variation. The algorithm resizes the transistor widths to ensure the speed of a circuit with a certain degree of confidence considering both inter- and intra-die process variations while keeping area and power budget within a limit.
Degree
Ph.D.
Advisors
Roy, Purdue University.
Subject Area
Electrical engineering
Off-Campus Purdue Users:
To access this dissertation, please log in to our
proxy server.