Design and optimization of multiple threshold CMOS for low power and high performance applications

Liqiong Wei, Purdue University

Abstract

The need for low power dissipation in portable computing and wireless communication systems is making design communities accept low voltage CMOS processes. With the lowering of supply voltage, the transistor threshold voltage has to be scaled down to meet the performance requirements. Unfortunately, such scaling increases the sub-threshold leakage current through a transistor, thereby increasing leakage power. Multiple-threshold voltages can be used to reduce the sub-threshold leakage current while maintaining performance. We propose several multiple Vth CMOS design techniques for leakage control in deep sub-micron IC's. One such technique is dual threshold CMOS design, which can reduce leakage power by assigning a high threshold voltage to some transistors in noncritical paths while using low-threshold transistors in the critical path(s) to achieve high performance. In order to achieve the best leakage power saving under a target performance constraint, several transistor-level and gate-level dual-Vth CMOS design algorithms are presented for selecting and assigning an optimal high threshold voltage. Results show that dual threshold technique is good for leakage power reduction during both standby and active modes. As an extension, dual-Vth technique is combined with dual-Vdd design technique to reduce both dynamic power and static power. In order to optimize the low voltage CMOS circuits, a TILOS-like sensitivity-based algorithm is provided for simultaneous gate-sizing and dual-Vth assignment. We also investigated the possibility of dynamically controlling the threshold voltage of transistor to achieve high performance in active mode while achieving low-power dissipation during the stand-by mode of operation. Dynamic threshold CMOS can be achieved using asymmetric double gate SOI MOSFETs, whose threshold voltage can change dynamically to suit the operating state of the circuit. Results show that double gate dynamic threshold SOI CMOS circuits provide the best power delay product.

Degree

Ph.D.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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