ACCLIB: Accelerators as libraries

Yue Du, Purdue University

Abstract

Accelerator based computing is a popular design paradigm employed by designers to help meet the power-performance requirements of modern System-on-chips (SoCs). However, the non-recurring costs (hardware design, HW/SW integration, logic and physical design, and mask generation) required to design SoCs have significantly increased, to the point where only very high-volume products are now able to invest in accelerator-based computing. The recent emergence of re-configurable SoC platforms promises to make accelerator based computing accessible to a much wider range of applications by eliminating some of these costs. However, the significant effort involved in identifying functions to accelerate, designing hardware implementations of these functions, and integrating them with software, remains a major bottleneck to mainstream adoption of accelerator based computing. Much effort has been devoted to technologies (such as HW/SW partitioning, behavioral synthesis, and interface generation) that enable an automated top-down design flow from system-level specifications. Unfortunately, these technologies have seen very limited adoption in practice since (i) there exists a large gap in quality (performance, power, etc.) between manually designed RTL and RTL generated by behavioral synthesis, and (ii) they address specific steps in the process of accelerator design and use, leaving other steps to still be manually performed. ^ In this work we propose a new design paradigm in which accelerators are viewed as libraries, and develop a design automation framework, ACCLIB, to realize our proposal. We envision pre-designed libraries of accelerators for various common compute-intensive functions (motivated by the emergence of open-source hardware repositories and commercial IP libraries). These libraries take full advantage of the capability of human designers to design highly efficient hardware, while relegating accelerator design effort to a one-time cost. Software developers simply indicate compute-intensive program regions as acceleration targets. Our framework employs powerful software verification techniques to automatically “match” acceleration targets against the library of hardware accelerators, automatically generates the required HW/SW interfaces (bus interface for the hardware, and software routines that communicate with the accelerator), and also transforms the program to utilize the accelerator. The framework enables software developers to transparently utilize hardware accelerators, thereby greatly simplifying their use and making accelerator based computing accessible to a much wider range of design teams. We validated our methodology by applying it to accelerate five benchmark programs using a library consisting of 15 hardware accelerators for commonly used compute-intensive functions.^

Degree

M.S.E.C.E.

Advisors

Anand Raghunathan, Purdue University.

Subject Area

Engineering, Computer

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