Circuit-architecture co-design for low power and system lifetime enhancement through voltage over-scaling

Georgios Karakonstantis, Purdue University

Abstract

Temporal performance degradation due to Negative Bias Temperature Instability (NBTI) and corresponding lifetime enhancement has emerged as a critical challenge in design of integrated circuits (ICs) in the nanometer technology nodes. The existing circuit level NBTI estimation approaches have neglected the inter-dependency of parameters such as voltage and temperature and their impact on the circuit lifetime. In this thesis we present a model that self-consistently estimates the NBTI degradation in circuits by considering these parameters simultaneously. Using the proposed model, we observe that a circuit with lower voltage can provide better lifetime performance than with higher voltage. This interesting observation can be attributed to the reduction of electric field in the transistor along with the circuit power/temperature reduction that leads to lesser NBTI degradation. Based on this observation we have developed on-line detection and mitigation schemes that allow voltage over-scaling to enhance the system lifetime. Specifically, voltage over-scaling is achieved by utilizing circuit/architecture design techniques based on “elastic clocking” and “unequal error protection of computations”. By trading off minor system throughput penalty in general purpose processors or minor output quality degradation in application specific processors for voltage over-scaling, we can achieve system lifetime enhancement and lower power consumption.

Degree

M.S.E.C.E.

Advisors

Roy, Purdue University.

Subject Area

Electrical engineering

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