NanoMOS 4.0: A tool to explore ultimate Silicon transistors and beyond
Abstract
This thesis discusses the modeling of nano-scale field-effect transistors using nanoMOS 4.0. Our goal is to present the reader with a comprehensive documentation of nanoMOS 4.0 including its code structure in detail, development history, and new features. As silicon device scaling is reaching its limit, nanoMOS 4.0 is able to simulate the ultimate Si transistor performance and explore new non-silicon based devices. In this report, we focus on a simple double-gate thin-body structure for demonstration purposes. One primary aim is to show how theories are incorporated computationally into a fully functional simulator. Physically, two main transport modules of nanoMOS, semi-classical (drift-diffusion and ballistic) and NEGF, are examined in detail including the driving theories behind them; computationally, we further discuss several important numerical issues and document "tricks of the trade" used in nanoMOS to resolve those issues. We present auxiliary programs such as a benchmark and testing suite and discuss how they are used to support the development of nanoMOS. In the end, we demonstrate the application of nanoMOS to real devices fabricated by the Intel Corporation to illustrate the methods used to benchmark simulation results against experimental data. Thus, with this report, we deliver a deeper understanding and comprehensive review of this tool to its user.
Degree
M.S.E.C.E.
Advisors
Klimeck, Purdue University.
Subject Area
Electrical engineering|Nanotechnology
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