Performance feedback scheduling: Harnessing hardware performance counters for performance improvements in multi-core scheduling

Stephen V Ziemba, Purdue University

Abstract

The multi-core era has led to a paradigm shift in the interaction between software and hardware. Multiple cores have replaced clock speed increases as the predominate means of performance improvement. The scheduler plays an increasingly important roll in system performance. The current Linux scheduler has changed little since the single core era except for the addition of load balancing. While it is necessary to keep each core busy for good performance, antiquated control mechanisms such as priority limit how threads can be scheduled and interact. This paper analyzes the impact of scheduling decisions on dynamic task performance and attempts to utilize runtime data to facilitate performance improvements. Performance behavior is analyzed utilizing support workloads from SPECWeb 2005. Hardware performance counter data is collected via extending the Linux scheduler and analysis is then performed. The results show that considering a single per-core metric (such as IPC or cache miss rate) is not sufficient to categorize application behavior. Additionally, threads perform differently based on the scheduling environment (thread run before current thread and what is scheduled on other cores) and the length of their time slices. Feedback is used to attempt to improve performance of several of the PARSEC benchmarks. However, deficiencies in performance counter API, lack of appropriate workloads and problems with timer/interrupt accounting made getting performance improvements not possible. Performance gains can be made feasible with a few suggested changes to the performance counter API to make overhead and accuracy more manageable.

Degree

M.S.E.C.E.

Advisors

Pai, Purdue University.

Subject Area

Computer Engineering

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