Benchmarking proposed logic technologies against silicon CMOS

Yunfei Gao, Purdue University

Abstract

More and more novel devices are being proposed these days. They have advantages in the some device physics aspects over each others. However the these characteristics don’t necessarily translate into better circuit-level features correspondingly. This work develops a consistent benchmark methodology for novel devices from circuit perspective. We use a 2-input FO4 NAND gate chain to evaluate the a set of metrics representing the performance and power consumption of a realistic 45nm CMOS technology with the SPICE simulation. We also benchmark a reasonable 15nm CMOS in the same way to investigate the circuit-level effects as the Silicon technology keeps scaling down. Other new technologies can also be benchmarked in the same framework and compared with the CMOS results. As building the SPICE models of the devices may be time-consuming, a new idea of circuit-level assessment is introduced in this work. The tool PETE (Purdue Explorotary Technology Evaluator) can take the I-V,C-V datas as the input and simulate the DC and AC characteristics of several logic gates, ring oscillator and carry adder. The devices can be investigated at the early stage of their development and compared with each other to see the circuits performance-power trade-off. In this work, the 45nm CMOS is reassessed with PETE and the results obtained are within 5% accuracy compared to the previous SPICE simulation. As an realistic case study, we investigate the carbon nanotubes field effect transistor (CNTFET) with PETE and make a comparison between the CNT MOSFETs and CNT BTBT FETs in sub-threshold operation from a circuit perspective and conclude that CNT BTBT FETs may have advantage over CNT MOSFETs in the low power sub-threshold logic operation.

Degree

M.S.E.C.E.

Advisors

Lundstrom, Purdue University.

Subject Area

Electrical engineering

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