Multi-scale simulations for high efficiency low power nanoelectronic devices
Abstract
Silicon based CMOS technology has been the driven force for semiconductor industry for decades. With higher degree of integration, transistors working under low supply voltage are desired to reduce power consumption. FinFET has been introduced to suppress the short channel effects and quantum tunneling; devices like Tunneling FET (TFET) and Piezoelectronic Transistor have been designed to achieve the subthreshold swing (SS) below 60mV/dec; novel memory cells like conductive bridging RAM (CBRAM) are able to operate at lower voltages and are more scalable than flash memory. In this work, several emerging logic and memory devices have been studied. The devices are optimized for high efficiency low power applications. Non-equilibrium Green’s function formalism with empirical tight binding (ETB) basis is used for quantum transport. The scaling of InGaAs FinFET is studied within virtual crystal approximation in the ballistic limit. The effects of random alloy scattering are discussed. The heterojunction TFETs are designed to achieve both low SS and high on-current. SmSe is parameterized to reproduce the metal insulator transition in Piezoelectronic Transistor. Copper is parameterized with the environmental dependent tight binding model and used for the study of grain boundary resistance in interconnects. Finally to study the resistive switching of CBRAM, functionalities to import structures generated by Molecular Dynamics simulations and perform quantum transport have been developed. Calculations are done with efficient offloading scheme to accommodate the memory and speed requirements for realistic geometries.
Degree
Ph.D.
Advisors
Klimeck, Purdue University.
Subject Area
Electrical engineering|Condensed matter physics|Nanotechnology
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